I cover topics about low power and mobile applications in the past years but there is something that is often neglected. It comes at the expense of lowering the power and it is performance. We can argue that minimizing power consumption is dependent on what kind of power we’re reducing (for example static or leakage vs. dynamic power) and its effect of the performance but we know that there is no void in physics and Higher Voltage threshold for example reduces leakgae but affects max performance.
The problem we have is that as much as we need lower leakage power and lower dynamic power to prolonge the battery life between charges, we also need high performance as we don’t want to wait for an application to load itself or transfer data to our mobile device.
As part of my role I track the operating performance of Image sensors and Displays and one of the good measurements is the maximum bandwidth used by the camera interface CSI-2 and display interface DSI.
I discussed this with David Wolfe (reference my interview with David here) and he provided me some statistics observed as part conducting interoeprability events in the past years.
The first diagram below shows the average speed per lane at each of the past 4 MIPI Display Interop Workshops. It gives us an interesting snapshot of the progress of MIPI DPHY devices, and we see that the speed per lane is steadily increasing.
The second diagram shows the average throughput of each device at the last 4 MIPI Display Interop Workshops. In this case, throughput is simply Mbps per lane times the number of lanes. You can see at the 2012 event throughput took a big jump ahead, largely due to the number of 4 lane devices.
It shows us an interesting trend in the type of demand that exists for MIPI DPHY displays that newer displays use higher bandwidth to achieve higher resolutions.
That’s not a surprise by any mean and we see this in the mobile devices exist in today’s market. What is means is that if you are developing an SoC and target to connect to cameras and displays, you better have flexibility in the maximum number of lanes supported to cover both low and high resolution cameras and displays. In addition you need to select carefully the IP you’re using and for your 28nm SoC design support for the 1.5Gbps possible with the D-PHY v1.1 specification is highly desired. Check out this page for more information about D-PHY capabilities covering performace up to 1.5Gbps/lane.
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